MULTI-FPGA PROTOTYPING OF AN ASIC CIRCUIT

摘要

The invention concerns a method of designing a prototype comprising a plurality of programmable chips, such as FPGA chips, for modelling an ASIC circuit, said ASIC circuit being intended to implement a logic design comprising a hierarchy of logic modules communicating together. The method according to the invention comprises the steps of:—partitioning the hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimising:—inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips;—and the number of crossings of programmable chips of a critical combinatorial path;—establishing a routing of the signals between programmable chips using the physical resources available.