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INTEGRATED CIRCUIT CHIP RELIABILITY USING RELIABILITY-OPTIMIZED FAILURE MECHANISM TARGETING

机译:使用可靠性优化的故障机制定位的集成电路芯片可靠性

摘要

Disclosed are methods for improving integrated circuit (IC) chip reliability. IC chips are manufactured and sorted into groups corresponding to process windows within a process distribution for the design. Group fail rates are set for each group based on failure mechanism fail rates, which are set for multiple failure mechanisms. An overall fail rate is determined for the full process distribution based on the group fail rates. First contribution amounts of the groups to the overall fail rate and second contribution amounts of the failure mechanisms to the group fail rate of each group are determined. Based on an analysis of the contribution amounts, at least one specific failure mechanism is selected and targeted for improvement (i.e., changes directed to the specific failure mechanism(s) are proposed and implemented). Optionally, proposed change(s) are only implemented if they will be sufficient to meet a reliability requirement and/or will not be cost-prohibitive.
机译:公开了用于提高集成电路(IC)芯片可靠性的方法。制造IC芯片并将其分类为与设计中的过程分布内的过程窗口相对应的组。根据故障机制的故障率为每个组设置组故障率,故障率是针对多个故障机制设置的。根据组故障率确定整个过程分配的总体故障率。确定各组对总故障率的第一贡献量和各故障机制对各组的故障率的第二贡献量。基于对贡献量的分析,至少一个特定的故障机制被选择并针对改进目标(即,提出并实施针对特定故障机制的改变)。可选地,仅在足以满足可靠性要求和/或不会抑制成本的情况下才实施建议的更改。

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