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Hybrid polymoprhic inline cache and branch target buffer prediction units for indirect branch prediction for emulation environments
Hybrid polymoprhic inline cache and branch target buffer prediction units for indirect branch prediction for emulation environments
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机译:混合多态内联高速缓存和分支目标缓冲区预测单元,用于仿真环境的间接分支预测
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摘要
Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.
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