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Staggered DLL clocking on N-Detect QED to minimize clock command and delay path
Staggered DLL clocking on N-Detect QED to minimize clock command and delay path
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机译:N-Detect QED上的交错DLL时钟可最大限度地减少时钟命令和延迟路径
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摘要
Apparatuses and methods are described for meeting timing and latency requirements using staggered clocking within the command path. In one example, an apparatus is disclosed that includes a timing circuit configured to provide an internal clock signal; a clock stagger circuit configured to receive the internal clock signal from the timing circuit and to generate at least one delayed internal clock signal; and a shift circuit arranged in a command decode and delay path of a command signal, coupled to the timing circuit and to the clock stagger circuit, and configured to capture the command from an external clock domain into an internal clock domain based on one or both of the internal clock signal and the delayed internal clock signal
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