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SELECTIVE COUPLING OF POWER RAILS TO A MEMORY DOMAIN(S) IN A PROCESSOR BASED SYSTEM
SELECTIVE COUPLING OF POWER RAILS TO A MEMORY DOMAIN(S) IN A PROCESSOR BASED SYSTEM
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机译:在基于处理器的系统中,电源轨到内存域的选择性耦合
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摘要
Selective coupling of power rails to memory domain(s) in processor based system such as to reduce or avoid the need to provide intentional decoupling capacitance in logic domain(s) is disclosed. To avoid or reduce providing additional intentional decoupling capacitance in logic domain to mitigate voltage droops on logic power rail power rail selection circuit is provided. The power rail selection circuit is configured to couple memory domain to a logic power rail when the logic power rail can satisfy a minimum operating voltage of memory arrays. The additional intrinsic decoupling capacitance of the memory arrays is coupled to the logic power rail. However if the operating voltage of the logic power rail is scaled down below the minimum operating voltage of the memory arrays when the logic domain does not need higher operation functionality the power rail selection circuit is configured to couple the memory domain to separate memory power rail.
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