PROCESS VERIFICATION APPARATUS USING SPATIOTEMPORAL LOGIC AND PROCESS SPECIFICATION

摘要

The present invention relates to a process verification apparatus. The process verification apparatus enables visual expression of a process specified through a formal technique, simulates and calculates the number of executable cases of the process, detects errors occurring while the process is executed, and verifies the requirements of the process through spatiotemporal logics. According to the present invention, the process verification apparatus enables visual expression of the specification of the process, simulates and calculates the number of executable cases of the visualized process, and detects the errors occurring when the process is executed, thereby enhancing the reliability of the process. Also, the process verification apparatus verifies the requirements of the process such as the dependent relationships between processes through verification symbols expressed in time and space to verify the requirements of the process visually.;COPYRIGHT KIPO 2017