METHODS FOR CELL PHASING AND PLACEMENT IN DYNAMIC ARRAY ARCHITECTURE AND IMPLEMENTATION OF THE SAME

摘要

A semiconductor chip is defined to include a logic chip region having a first chip level at which layout quality features are arranged according to a first virtual grate and a second chip level at which layout features are arranged according to a second virtual layout. There is a free space relationship between the first and second virtual grates. A plurality of cells are disposed in the logic block region. Each of the plurality of cells is defined according to an appropriate one of a plurality of cell phases. A suitable cell phase allows the layout features at the first and second chip levels of a given cell to be aligned with the first and second virtual grit located within a given positioned cell.