リセット回路、基準電圧生成回路

摘要

PROBLEM TO BE SOLVED: To reset a circuit which refers to a reference voltage, when the reference voltage is unstable because a supply voltage is low and to cancel the reset of the circuit which refers to the reference voltage, when the reference voltage is stably outputted because the supply voltage is sufficiently high.;SOLUTION: A PMOS transistor MP35 having a gate connected to an anode of a diode D3 and an NMOS transistor MN33 are connected in series. An NMOS transistor MN32 and a PMOS transistor MP32 are connected in series. At a reset signal terminal TB, a voltage between the NMOS transistor MN 32 and the PMOS transistor MP32 is outputted as a reset signal RSTB. A forward bias voltage Vd3 of the diode D3 is equal to or higher than a forward bias voltage Vd1 of a diode D1. A gate-source voltage Vtp1 of a PMOS transistor MP21 is equal to or higher than a gate-source voltage Vtp2 of the PMOS transistor MP35.;SELECTED DRAWING: Figure 1;COPYRIGHT: (C)2019,JPO&INPIT