Serial data communications using a UART module and method therefor

摘要

A data processing system includes a universal asynchronous receive/transmit (UART) module and timer module. The UART module has a first input terminal for receiving an input clock signal, a second input terminal for receiving a receive data signal, and an output terminal for providing a transmit data signal. The receive data signal and the transmit data signal use a baud rate based clock signal determined using the input clock signal, and wherein the output terminal and the second input terminal are coupled together for communicating data with a universal synchronous asynchronous receiver/transmitter (USART) module. The timer module is coupled to receive the input clock signal. The timer module provides a duplicate baud rate clock signal for communication to the USART module. The duplicate baud rate clock signal is substantially the same as the baud rate based clock signal.