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PRODUCING MODELS FOR DYNAMICALLY DEPLETED TRANSISTORS USING SYSTEMS HAVING SIMULATION CIRCUITS

机译:使用具有仿真电路的系统的动态损耗晶体管的生产模型

摘要

A simulation circuit, that simulates characteristics of transistors is produced to include: an isolation body resistor representing resistance of a channel isolation portion of a transistor; a main body resistor representing resistance of main channel portion of the transistor; an isolation transistor connected to the isolation body resistor; and a body-contact transistor connected to the main body resistor. Simulated data is generated by supplying test inputs to the simulation circuit, while selectively activating either the isolation transistor or the body-contact transistor. Test data is generated by supplying the test inputs to the transistors, and measuring output of the transistors. The simulated data is compared to the test data to identify data differences. The design of the transistors is changed to reduce the data differences. The generation of test data, comparing, and design changes are repeated, until the data differences are within a threshold.
机译:产生模拟晶体管特性的模拟电路,其包括:代表晶体管的沟道隔离部分的电阻的隔离体电阻器;主体电阻,代表晶体管的主沟道部分的电阻;隔离晶体管,与隔离体电阻相连;体接触晶体管连接到主体电阻。通过向模拟电路提供测试输入,同时选择性地激活隔离晶体管或体接触晶体管,来生成模拟数据。通过将测试输入提供给晶体管并测量晶体管的输出来生成测试数据。将模拟数据与测试数据进行比较,以识别数据差异。改变晶体管的设计以减少数据差异。重复测试数据的生成,比较和设计更改,直到数据差异在阈值之内。

著录项

  • 公开/公告号US2019163853A1

    专利类型

  • 公开/公告日2019-05-30

    原文格式PDF

  • 申请/专利权人 GLOBALFOUNDRIES INC.;

    申请/专利号US201715822661

  • 发明设计人 ANUPAM DUTTA;TAMILMANI ETHIRAJAN;

    申请日2017-11-27

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 12:06:58

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