Apparatus and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

摘要

Apparatuses and methods for concurrently performing memory access operations on multiple memory planes are disclosed herein. The example method may include receiving first and second instruction and address pairs of a memory associated with the first and second planes, respectively. The method provides, in response to receiving the first and second instruction and address pairs, providing first and second read voltages based on the first and second page types determined from the first and second instruction and address pairs. It may further comprise a step. The method may further comprise configuring the first GAL decoder circuit to provide either a first read voltage or a pass voltage on each GAL of the first GAL bus. The method may further comprise configuring the second GAL decoder circuit to provide one of a second read level voltage signal or a pass voltage signal on each GAL of the second GAL bus coupled to the second memory plane.