首页>
外国专利>
Method of providing protective cavity and integrated passive components in wafer level chip scale package using a carrier wafer
Method of providing protective cavity and integrated passive components in wafer level chip scale package using a carrier wafer
展开▼
机译:使用载体晶片在晶片级芯片规模封装中提供保护腔和集成无源组件的方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
A wafer-level chip-scale package includes a body, a conductive via passing through the body, a contact bump formed at a lower portion of the body and in electrical connection with a lower end of the conductive via, a piezoelectric substrate directly bonded to an upper end of the conductive via, and a cavity defined between a portion of the body and the piezoelectric substrate.
展开▼