The present invention relates to the digital circuits for evaluating neuralengineeringframework style neural networks. The digital circuits for evaluating neuralengineeringframework style neural networks comprised of at least one on-chip memory, apluralityof non-linear components, an external system, a first spatially parallelmatrixmultiplication, a second spatially parallel matrix multiplication, an errorsignal,plurality of set of factorized network weight, and an input signal. Theplurality of setsof factorized network weights further comprise a first set factorized networkweightsand a second set of factorized network weights. The first spatially parallelmatrixmultiplication combines the input signal with the first set of factorizednetwork weightscalled the encoder weight matrix to produce an encoded value. The non-linearcomponents are hardware simulated neurons which accept said encoded value toproduce a distributed neural activity. The second spatially parallel matrixmultiplicationcombines said distributed neural activity with said second set of factorizednetworkweights called the decoder weight matrix to produce an output signal.
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