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VIA ETCHING METHOD AND CIRCUIT DETECTION METHOD FOR THIN FILM TRANSISTOR ARRAY SUBSTRATE

机译:薄膜晶体管阵列基板的蚀刻方法和电路检测方法

摘要

A via etching method and a circuit detection method for a thin film transistor array substrate. The via etching method comprises: adjusting an included angle between a base supporting a sample to be etched and the center of an ion beam for etching said sample to a preset angle of greater than 0 degrees and less than 90 degrees (S101); and etching a second film layer and a first film layer of said sample until an etched surface of the first film layer is sloped relative to a surface of the base so as to form a via extending through the second film layer and partially extending through the first film layer in the thickness direction thereof (S102). The invention prevents over-etching or under-etching of a first film layer, such that the first film layer can be effectively exposed at a via, thereby ensuring favorable electrical contact between an electrode subsequently formed in the via and the first film layer.
机译:用于薄膜晶体管阵列基板的通孔蚀刻方法和电路检测方法。所述通孔蚀刻方法包括:将支撑要蚀刻的样品的基底与用于蚀刻所述样品的离子束的中心之间的夹角调节为大于0度且小于90度的预设角度(S101);蚀刻所述样品的第二膜层和第一膜层,直到所述第一膜层的蚀刻面相对于所述基底的表面倾斜,以形成延伸穿过所述第二膜层并部分延伸穿过所述第一膜层的通孔膜层沿其厚度方向(S102)。本发明防止了第一膜层的过度蚀刻或蚀刻不足,从而可以在通孔处有效地暴露第一膜层,从而确保随后形成在通孔中的电极与第一膜层之间的良好的电接触。

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