AT-SPEED -- SYSTEM-ON-CHIP FOR AT-SPEED TEST OF LOGIC CIRCUIT AND OPERATING METHOD THEREOF

摘要

The present invention provides a system-on-chip for AT-SPEED test of a logic circuit and a method of operation thereof. A system-on-chip including a plurality of cores according to an embodiment of the present invention includes a first scan register and a first scan included in a first core among a plurality of cores and closest to an input port of the first core And an inverting circuit positioned on the feedback path of the register, a second scan register included in the first core, and a logic circuit positioned on the data path between the first scan register and the second scan register, and AT of the logic circuit In the test mode for SPEED test, the inverting circuit inverts the scan data output from the first scan register to generate test data, and the first scan register stores test data in response to the first pulse of the clock, The logic circuit outputs result data based on the test data output from the first scan register, and the second scan register stores the result data in response to the second pulse of the clock.