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Using runtime information from solvers to measure quality of formal verification

摘要

Systems and techniques are described for using runtime information to identify a verification hole and/or compute a verification metric. Runtime information (RI) for a set of proven assertions can be determined, wherein the RI includes a first set of registers, a first set of inputs, and a first set of constraints that were used by a formal verification engine during runtime to prove one or more assertions for a design under verification (DUV). Next, a second set of registers, a second set of inputs, and a second set of constraints that are not present in the RI can be determined. The second set of registers, the second set of inputs, and/or the second set of constraints can then be used to (1) identify a verification hole and/or (2) compute a verification metric.

著录项

  • 公开/公告号US10657307B1

    专利类型

  • 公开/公告日2020.05.19

    原文格式PDF

  • 申请/专利权人

    申请/专利号US16023849

  • 申请日2018.06.29

  • 分类号

  • 国家 US

  • 入库时间 2022-08-21 10:58:30

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