Inductor-less divide-by-3 injection locked frequency divider

摘要

A frequency divider circuit includes an oscillator comprising a plurality of delay elements coupled in series with each other, a first coupling circuit coupled to a first oscillator node and including a control terminal to receive a first retiming signal, and a first multiplexer including inputs coupled to receive the input signal and a complementary input signal, a control terminal coupled to a second oscillator node, and an output to provide the first retiming signal. The first multiplexer may be configured to alternate between injecting the input signal into the first oscillator node based on rising edges of the input signal and injecting the input signal into the first oscillator node based on falling edges of the input signal in response to a logic state of an oscillation waveform appearing at the second oscillator node.