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Design of a Delayless Feedback Path Free 2nd-order Two-Path Time-Interleaved Discrete-Time Delta-Sigma Modulator- a New Approach

机译:无延迟反馈路径自由的二阶两路径时间交错离散时间Δ-Σ调制器的设计-一种新方法

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摘要

This paper presents the design procedure for a 2nd_order two-path Discrete-Time Time-Interleaved (DTTI) ΔΣ modulator from a conventional single-loop 2nd-order Discrete-Time (DT) ΔΣ modulator through the use of time domain equations and time-interleaving concepts [1]. The resulting modulator is free from the delayless feedback path and has only one set of integrators. The delayless feedback path issue in Time-Interleaved (TI) ΔΣ modulators is a critical restriction for the implementation of TI ΔΣ modulators and is effectively eliminated through the use of the approach proposed in this paper. The DTTI ΔΣ modulator requires only three op-amps and two quantizers both of which work concurrently, in comparison to the single-loop DT counterpart that also deploys two op-amps. For an OverSampling Ratio (OSR) of 16 and a clock frequency of 640MHz, our simulation results show a maximum Signal-to-Noise Ratio (SNR) for the DTTI ΔΣ modulator to be 70.5dB with an input bandwidth of 20MHz which has 15dB improvement in comparison to its single-loop, single-path DT counterpart.
机译:本文通过使用时域方程和时域方程,介绍了传统单环二阶离散时间(DT)ΔΣ调制器的二阶二路径离散时间交错(DTTI)ΔΣ调制器的设计过程。交错概念[1]。所得的调制器没有无延迟反馈路径,并且只有一组积分器。时间交错(TI)ΔΣ调制器中的无延迟反馈路径问题是TIΔΣ调制器实现的关键限制,可通过使用本文提出的方法有效消除。与也部署了两个运算放大器的单回路DT相比,DTTIΔΣ调制器仅需要三个运算放大器和两个量化器即可同时工作。对于16的过采样率(OSR)和640MHz的时钟频率,我们的仿真结果表明DTTIΔΣ调制器的最大信噪比(SNR)为70.5dB,输入带宽为20MHz,改善了15dB与它的单回路,单路径DT相比。

著录项

  • 作者

    Talebzadeh J.; Kale I.;

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  • 年度 2017
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  • 正文语种 en
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