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Novel Architecture of 17 Bit Address RISC CPU with Pipelining Technique Using Xilinx in VLSI Technology

机译：采用Xilinx在VLsI技术中采用流水线技术的17位地址RIsC CpU的新架构

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Rakesh M. R; Ajeya B;
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年度 2014
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1. Novel Architecture of 17 Bit Address RISC CPU with Pipelining Technique Using Xilinx in VLSI Technology [J] . Rakesh M. R, Ajeya B, Mohan A.R International Journal of Engineering Research and Applications . 2014 ,第5期

机译：在VLSI技术中使用Xilinx采用流水线技术的17位地址RISC CPU新型体系结构
2. Design Of Pipelined RISC MIPS Processor Using VLSI Technology [J] . Nyamatulla M Patel, Sachin S Patil, Mamata A Navi, International Journal of Engineering Research and Applications . 2018 ,第9期

机译：基于VLSI技术的流水线RISC MIPS处理器设计
3. Verilog Implementation of a MIPS RISC 32-bit Pipelined Processor Architecture [J] . P. Indira, Ved Vyas Dwivedi, M. Kamaraju IOSR Journal of Electronics and Communication Engineering . 2019 ,第1期

机译：MIPS RISC 32位流水线处理器体系结构的Verilog实现
4. Power Aware Study of 32-bit 5-stage Pipeline RISC CPU using 180nm CMOS Technology [C] . Pritesh Kumar Yadav, Prasanna Kumar Misra IEEE India Council International Conference . 2017

机译：使用180nm CMOS技术的32位5级流水线RISC CPU的电源感知研究
5. Exploring Lightweight Profiling Techniques in Modern CPU Architectures [D] . Wang, Qingsen. 2019

机译：探索现代CPU架构中的轻质分析技术
6. An Integrated Pipeline of Open Source Software Adapted for Multi-CPU Architectures: Use in the Large-Scale Identification of Single Nucleotide Polymorphisms [O] . B. Jayashree, Manindra S. Hanspal, Rajgopal Srinivasan, 2007

机译：适用于多CPU体系结构的开放源代码软件集成管道：用于大规模鉴定单核苷酸多态性
7. RISC Processor Design in VLSI Technology Using the Pipeline Technique [O] . Rakesh M.R 2015

机译：使用流水线技术的VLSI技术中的RISC处理器设计

Novel Architecture of 17 Bit Address RISC CPU with Pipelining Technique Using Xilinx in VLSI Technology

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