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Monolithic electronic-photonic integration in state-of-the-art CMOS processes

机译:采用最先进的CmOs工艺实现单片电子光子集成

摘要

As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. Photonic devices promise to break this bottleneck with superior bandwidth-density and energy-efficiency. Initial work by many research groups to adapt photonic device designs to a silicon-based material platform demonstrated suitable independent performance for such links. However, electronic-photonic integration attempts to date have been limited by the high cost and complexity associated with modifying CMOS platforms suitable for modern high-performance computing applications. In this work, we instead utilize existing state-of-the-art electronic CMOS processes to fabricate integrated photonics by: modifying designs to match the existing process; preparing a design-rule compliant layout within industry-standard CAD tools; and locally-removing the handle silicon substrate in the photonic region through post-processing. This effort has resulted in the fabrication of seven test chips from two major foundries in 28, 45, 65 and 90 nm CMOS processes. Of these efforts, a single die fabricated through a widely available 45nm SOI-CMOS mask-share foundry with integrated waveguides with 3.7 dB/cm propagation loss alongside unmodified electronics with less than 5 ps inverter stage delay serves as a proof-of-concept for this approach. Demonstrated photonic devices include high-extinction carrier-injection modulators, 8-channel wavelength division multiplexing filter banks and low-efficiency silicon germanium photodetectors. Simultaneous electronic-photonic functionality is verified by recording a 600 Mb/s eye diagram from a resonant modulator driven by integrated digital circuits. Initial work towards photonic device integration within the peripheral CMOS flow of a memory process that has resulted in polysilicon waveguide propagation losses of 6.4 dB/cm will also be presented.
机译:随着硅CMOS晶体管的规模化,增加了单个芯片上计算的密度和能效,与存储器的片外通信链接已成为现代处理器的主要瓶颈。光子器件有望以优异的带宽密度和能效打破这一瓶颈。许多研究小组为使光子器件设计适应基于硅的材料平台所做的初步工作证明了此类链接具有合适的独立性能。但是,迄今为止,由于修改适用于现代高性能计算应用程序的CMOS平台相关的高成本和复杂性,电子光子集成尝试受到了限制。在这项工作中,我们改为利用现有的最先进的电子CMOS工艺来制造集成光子器件,方法是:修改设计以匹配现有工艺;在行业标准的CAD工具中准备符合设计规则的布局;通过后处理在光子区域中局部去除处理硅衬底。这项工作已导致两个主要代工厂以28、45、65和90 nm CMOS工艺制造了七个测试芯片。在这些努力中,通过广泛使用的45nm SOI-CMOS掩模共享代工厂制造的单个裸片具有集成的波导,该波导具有3.7 dB / cm的传播损耗,以及未经修改的电子器件,其反相器级延迟小于5 ps,可作为以下概念的证明这种方法。演示的光子器件包括高消光载流子注入调制器,8通道波分复用滤波器组和低效率硅锗光电探测器。通过记录由集成数字电路驱动的谐振调制器的600 Mb / s眼图,可以验证同时的电子光子功能。还将介绍在存储过程的外围CMOS流程中进行光子器件集成的初步工作,该过程已导致多晶硅波导的传播损耗为6.4 dB / cm。

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