Bandgap voltages references are widely used in IC design, but are sensitive to low-frequency noise and component mismatch. This thesis describes the design and testing of a new IC voltage reference that targets these issues through three dynamic element matching (DEM) subsystems. The first is a chopper OTA, and the second two are component rotation schemes: one to exchange the positions of two critical resistors, and the second to cycle through all BJTs, periodically selecting each to participate as the "1" transistor of the N:1 bandgap ratio. Practical designs that address the various switching issues typically associated with DEM, such as glitch and clock drift, are described. Analytic expressions for the effects of noise and mismatch throughout the bandgap reference are derived, along with expressions for calculating the improvement that can be achieved by DEM. A test chip was implemented in a 0.25[mu]m BiCMOS process; with its three DEM subsystems enabled it is shown to achieve a 20x 1/f noise improvement and a 34x mismatch error improvement.
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