Lattice mismatched compound semiconductors and devices on silicon

摘要

III-V compound semiconductors, due to their superior electron mobility, are promising candidates for n-type metal-oxide-semiconductor field effect transistors (MOSFETs). However, the limited size of III-V substrates and the degradation of IIIV MOSFET channel mobility remain two major challenges for III-V MOSFETs. The purpose of this thesis is to solve or partially solve these challenges. To create large diameter III-V materials, the synthesis of high quality III-V compound semiconductors (lattice-matched to InP) on Si substrates by metal-organic chemical vapor deposition (MOCVD) was studied. Epitaxy of III-V/Si (or Ge) may give rise to antiphase disorders due to the inequivalence of the two face-centered-cubic sublattices of III-V zinc-blende structures. By using a 60 offcut substrate (Ge on insulator) which favors a double-step surface reconstruction upon annealing, antiphase disorders were suppressed and single-domain GaAs on Si was demonstrated. The lattice was then graded from GaAs to InP by compositionally graded InxGa1-xAs-InyGa1-yP alloys and GaAsi-zSbz alloys, which introduce the strain gradually to promote dislocation propagation while suppressing nucleation. It was demonstrated that the phase separation in these pseudobinary alloys could be kinetically suppressed by the low surface diffusivity of adatoms during the non-equilibrium MOCVD process. This allowed us to achieve high quality InP on offcut GaAs. In addition, the dislocation kinetics of GaAs1-zSbz alloys was studied. The dislocation glide velocity of GaAs1-zSbz alloys was estimated to be 1 im/s at 575°C by fitting the experimental data with the dislocation propagation theory. The channel electron mobility of InP-based Ino.53GaO.47As quantum-well MOSFETs was studied by Hall measurements and the dominant scattering mechanisms were discussed. Although invariant for different gate dielectric (Al203) thicknesses, the mobility turns out to be strongly dependent on the barrier thickness, gate dielectric/barrier interfacial defect states and carrier density. To understand and quantify this dependence, a theoretical model based on internal phonon scattering and interfacial defect coulomb scattering was developed. The Born approximation, random-phase approximation, and two-dimensional limit for carriers were assumed for the coulomb scattering. The results of this model are in good agreement with the experimental data, and the predictions from this model shed light on future MOSFET design and synthesis.