The phenomenal success in the manufacture of multi-layer, Ultra-Large-Scale-Integrated (ULSI) semiconductor devices is in part due to the local and global planarization capabilities of the chemical-mechanical polishing (CMP) process. At present, copper is widely used as the interconnect material in the ULSI technology. The greatest challenge in Cu CMP now is the control of wafer surface non-uniformity-primarily due to dielectric erosion and copper dishing at various scales--to within the ever stringent industry specifications. In this thesis, an integrated non-uniformity model is developed by combining wafer-, die- and feature-scale non-uniformities. A feature-scale pressure calculation scheme based on surface step-height is adopted, and the evolution of the surface in each polishing stage is modeled in terms of geometric, material and process parameters. Various pad/wafer contact mechanics regimes have been considered to model oxide erosion and Cu dishing, from submicron device level to the global wiring level. The plausible causes of erosion and dishing at wafer-, die- and feature-scales were identified and integrated into the feature-scale step-height models. Such parameters include: initial pattern geometry, wafer-scale uniformity, and Cu-to-oxide slurry selectivity, material properties, and surface topography of the pad. Based on the developed erosion and dishing models, the effects of model parameters on the wafer-surface non-uniformity in Cu CMP are discussed, and parameter sets to satisfy both dishing and erosion specifications are obtained.
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