Design and characterization of Si/SiGe heterostructure sub-100 nm bulk p-MOSFET

摘要

As the gate length of CMOS device is scaled down to the sub-100 nanometer node, the development of devices faces many technological challenges, which are related to material and process integration. As a new channel material, compressively strained SiGe layer grown directly on the bulk Si is attractive for the p-MOSFET because of its integration compatibility with the Si-based process. The goal of this thesis is to design and fabricate bulk Si/SiGe heterostructure nano scale p-MOSFETs and characterize their performance. In designing the sub-100 nm Si/SiGe heterostructure devices, low temperature process is necessary because of the high diffusivity of Ge in the strained SiGe layer and shallow source/drain structure. In this work, nickel silicidation is used as a low temperature process for low resistance source/drain and fully silicided (FUSI) gate. E-beam lithography is used for patterning nano scale gate with hydrogen silsequioxane (HSQ) e-beam resist and proper cleaning process for CMOS process compatibility. Extraction of carrier transport parameters for deep submicron devices will be also discussed as a performance indicator for characterizing Si/SiGe heterostructure p-MOSFET with special consideration of strain and defect effects. The degradation of effective mobility and velocity was observed in nano-scale Si/SiGe p-MOSFETs. This is mainly due to the increased coulombic scattering by the increased doping concentration in the channel. The defects and strain relaxation are other two possible mechanisms of mobility degradation.