The effects of excess loop delay in continuous-time sigma-delta modulators

摘要

Continuous-time sigma-delta (CT-Sigma Delta) modulators have recently received great attention in the academia as well as in the industry. Despite the improved understanding of the operation of CT-Sigma Delta modulators, the problem due to excess loop delay that arises from timing mismatch and parasitic delay still remains unsolved. Thus, the thesis investigates the effects of the excess loop delay. In specific, the sensitivity of various CT-Sigma Delta topologies to the excess loop delay is explored by converting the CT modulators to its DT equivalents and realizing loop filters in state-space representations in MATLAB ©.