The Chemical-mechanical polishing (CMP) process is now widely employed in the ultralarge scale integration chip fabrication. Due to the continuous advances in semiconductor fabrication technology and decreasing sub-micron feature size, the characterization of erosion, which affects circuit performance and manufacturing throughput, has been an important issue in Cu CMP. In this paper, the erosion in Cu CMP is divided into two levels. The wafer-level and die-level erosion models were developed based on the material removal rates and the geometry of incoming wafers to the Cu CMP process, including the Cu interconnect area fraction, linewidth and Cu deposition thickness. Experiments were conducted to obtain the selectivity values between the Cu, barrier layer and dielectric, and the values of within-wafer material removal rate ratio, β, for the validation of the new erosion model. It was compared with the existing models and was found to agree better with the experimental data.
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