Experimental investigation and digital compensation of DGD for 112 Gb/s PDM-QPSK clock recovery

摘要

For asynchronous sampled systems such as Polarization Division Multiplexed Quadrature Phase Shift Keying, (PDM-QPSK), phase and frequency of the sampling clock is typically not synchronized to the data symbols. Therefore, timing adjustment, so called clock recovery and interpolation, must be performed in digital domain prior to signal demodulation in order to avoid cycle slips. For the first time, the impact of first order PMD, (DGD), is experimentally investigated and quantified for 112 Gb/s PDM-QPSK signal. We experimentally show that the combined effect of polarization mixing and first order PMD can significantly affect the performance of the timing error detector gain, even for moderate values leading to system outage. We propose and experimentally demonstrate a novel digital adaptive timing error detector is robust to polarization mixing and DGD. The proposed timing error detector algorithm combines the Gardner timing error detector algorithm with an adaptive structure based on gradient method.