This paper investigates the on-chip implementation of a frequency locked loop (FLL) over a VCO that decreases the phase noise and linearizes the transfer function. Implementation of the FLL inside a PLL is also investigated and a possible application is highlighted. Design of a special kind of low noise frequency detector without a reference frequency (frequency-to-voltage converter), which is the most critical component of the FLL, is also presented in a 0.25 mum BiCMOS process. Linearization and approximately 15 dBc/Hz phase noise suppression is demonstrated over a moderate phase noise LC VCO with a center frequency of 10 GHz.
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