Main memory has become one of the largest contributors tooverall energy consumption and offers many opportunities for power/energyreduction. In this paper, we propose a new memory organization, called{em Power-Aware Cached-DRAM} (PA-CDRAM), that integrates a moderatelysized cache directly into a memory device. We use this cache toturn a memory bank off immediately after a memory access to reduceenergy consumption. While other work has used CDRAM to improvememory performance, we modify CDRAM to reduce energy consumption.In this paper, we describe our memory organization and describethe challenges for achieving low energy consumption and how to addressthem. We evaluate the approach using a cycle accurate processor andmemory simulator. Our results show that PA-CDRAM achieves an average28% improvement in the energy-delay product when compared toa time-out power management technique.
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