Multi-level Memristive Memory with Resistive Networks

摘要

Analog memory is of great importance in neurocomputing technologies field,but still remains difficult to implement. With emergence of memristors in VLSItechnologies the idea of designing scalable analog data storage elements findsits second wind. A memristor, known for its history dependent resistancelevels, independently can provide blocks of binary or discrete state datastorage. However, using single memristor to save the analog value ispractically limited due to the device variability and implementationcomplexity. In this paper, we present a new design of discrete state memorycell consisting of subcells constructed from a memristor and its resistivenetwork. A memristor in the sub-cells provides the storage element, while itsresistive network is used for programming its resistance. Several sub-cells arethen connected in parallel, resembling potential divider configuration. Theoutput of the memory cell is the voltage resulting from distributing the inputvoltage among the sub-cells. Here, proposed design was programmed to obtain 10and 27 different output levels depending on the configuration of the combinedresistive networks within the sub-cell. Despite the simplicity of the circuit,this realization of multilevel memory provides increased number of outputlevels compared to previous designs of memory technologies based on memristors.Simulation results of proposed memory are analyzed providing explicit data onthe issues of distinguishing discrete analog output levels and sensitivity ofthe cell to oscillations in write signal patterns.