A real-time design based on FPGA for Expeditious Error Reconciliation in QKD system

摘要

For high-speed quantum key distribution systems, error reconciliation isoften the bottleneck affecting system performance. By exchanging commoninformation through a public channel, the identical key can be generated onboth communicating sides. However, the necessity to eliminate disclosed bitsfor security reasons lowers the final key rate. To improve this key rate, theamount of disclosed bits should be minimized. In addition, decreasing the timespent on error reconciliation also improves the key rate. In this paper weintroduce a practical method for expeditious error reconciliation implementedin a Field Programmable Gate Array for a discrete variable quantum keydistribution system, and illustrate the superiority of this method to othersimilar algorithms running on a PC. Experimental results demonstrate therapidity of the proposed protocol.