A Wrapper of PCI Express with FIFO Interfaces based on FPGA

摘要

This paper proposes a PCI Express (PCIE) Wrapper core named PWrapper withFIFO interfaces. Compared with other PCIE solutions, PWrapper has severaladvantages such as flexibility, isolation of clock domain, etc. PWrapper isimplemented and verified on Vertex -5-FX70T which is a development boardprovided by Xilinx Inc. Architecture of PWrapper and design of two key modulesare illustrated, which timing optimization methods have been adopted. Then weexplained the advantages and challenges of on-chip interfaces technology basedon FIFOs. The verification results show that PWrapper can achieve the speed of1.8Gbps (Giga bits per second).