Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture

摘要

Transaction Level Modeling (TLM) approach is used to meet the simulationspeed as well as cycle accuracy for large scale SoC performance analysis. Weimplemented a transaction-level model of a proprietary bus called AHB+ whichsupports an extended AMBA2.0 protocol. The AHB+ transaction-level model shows353 times faster than pin-accurate RTL model while maintaining 97% of accuracyon average. We also present the development procedure of TLM of a busarchitecture.