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Statistical compact model strategies for nano CMOS transistors subject of atomic scale variability

机译:纳米CmOs晶体管的统计紧凑模型策略受原子尺度变化影响

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摘要

One of the major limiting factors of the CMOS device, circuit and system simulation in sub 100nm regimes is the statistical variability introduced by the discreteness of charge and granularity of matter. The statistical variability cannot be eliminated by tuning the layout or by tightening fabrication process control. Since the compact models are the key bridge between technology and design, it is necessary to transfer reliably the MOSFET statistical variability information into compact models to facilitate variability aware design practice. The aim of this project is the development of a statistical extraction methodology essential to capture statistical variability with optimum set of parameters particularly in industry standard compact model BSIM. This task is accomplished by using a detailed study on the sensitivity analysis of the transistor current in respect to key parameters in compact model in combination with error analysis of the fitted Id-Vg characteristics. The key point in the developed direct statistical compact model strategy is that the impacts of statistical variability can be captured in device characteristics by tuning a limited number of parameters and keeping the values for remaining major set equal to their default values obtained from the “uniform” MOSFET compact model extraction. However, the statistical compact model extraction strategies will accurately represent the distribution and correlation of the electrical MOSFET figures of merit. Statistical compact model parameters are generated using statistical parameter generation techniques such as uncorrelated parameter distributions, principal component analysis and nonlinear power method. The accuracy of these methods is evaluated in comparison with the results obtained from ‘atomistic’ simulations. The impact of the correlations in the compact model parameters has been analyzed along with the corresponding transistor figures of merit. The accuracy of the circuit simulations with different statistical compact model libraries has been studied. Moreover, the impact of the MOSFET width/length on the statistical trend of the optimum set of statistical compact model parameters and electrical figures of merit has been analyzed with two methods to capture geometry dependencies in proposed statistical models.
机译:在100nm以下的制程中,CMOS器件,电路和系统仿真的主要限制因素之一是电荷的离散性和物质的粒度所引起的统计可变性。无法通过调整布局或加强制造过程控制来消除统计差异。由于紧凑型模型是技术与设计之间的关键桥梁,因此有必要将MOSFET统计可变性信息可靠地传输到紧凑型模型中,以促进意识到可变性的设计实践。该项目的目的是开发一种统计提取方法,该方法对于捕获具有最佳参数集的统计可变性至关重要,特别是在行业标准紧凑型模型BSIM中。通过对紧凑型模型中的晶体管电流相对于关键参数的灵敏度分析进行详细研究,并结合拟合的Id-Vg特性进行误差分析,可以完成此任务。所开发的直接统计紧凑模型策略的关键点在于,通过调整有限数量的参数并使其余主要集的值等于从“统一”获得的默认值,可以将统计变异性的影响捕获到设备特性中。 MOSFET紧凑模型提取。但是,统计紧凑模型提取策略将准确地表示电MOSFET品质因数的分布和相关性。使用统计参数生成技术(例如不相关的参数分布,主成分分析和非线性幂方法)生成统计紧凑模型参数。与从“原子”模拟获得的结果相比,评估了这些方法的准确性。已经分析了相关性对紧凑模型参数的影响以及相应的晶体管品质因数。研究了具有不同统计紧凑模型库的电路仿真的准确性。此外,已经使用两种方法来分析MOSFET宽度/长度对统计紧凑模型参数和电气品质因数的最佳集合的统计趋势的影响,这两种方法可以捕获拟议统计模型中的几何依赖性。

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  • 作者

    Moezi Negin;

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  • 年度 2012
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  • 原文格式 PDF
  • 正文语种 English
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