首页> 外文OA文献 >Fault characterization and testability considerations in multi-valued logic circuits.

【2h】

Fault characterization and testability considerations in multi-valued logic circuits.

机译：多值逻辑电路中的故障表征和可测试性考虑因素。

代理获取

本网站仅为用户提供外文OA文献查询和代理获取服务，本网站没有原文。下单后我们将采用程序或人工为您竭诚获取高质量的原文，但由于OA文献来源多样且变更频繁，仍可能出现获取不到、文献不完整或与标题不符等情况，如果获取不到我们将提供退款服务。请知悉。

页面导航

著录项
引文网络
相似文献
相关主题

著录项

作者
Al-Sharif Maher Mohammed Mahmoud;
展开▼
作者单位

展开▼
年度 1998
总页数
原文格式 PDF
正文语种 {"code":"en","name":"English","id":9}
中图分类

相似文献

外文文献
中文文献
专利

1. Fault characterization, testing considerations, and design for testability of BiCMOS logic circuits [J] . Salama A.E., Elmasry M.I. IEEE Journal of Solid-State Circuits . 1992,第6期

机译：故障表征，测试注意事项和BiCMOS逻辑电路的可测试性设计
2. Multi-valued Logic Mapping Of Resistive Short And Open Delay-fault Testing In Deep Sub-micron Technologies [J] . Reza Javaheri, Reza Sedaghat Microelectronics reliability . 2009,第2期

机译：深亚微米技术中的电阻性短路和开路延迟故障测试的多值逻辑映射
3. Identification of Influence of Part Tolerances of 1PWR-SE Pump on its Total Efficiency taking into consideration Multi-Valued Logic Trees [J] . Adam Deptu?a, Piotr Osiński, Marian A. Partyka Journal of Automation, Mobile Robotics & Intelligent Systems . 2018,第4期

机译：考虑多值逻辑树，确定1PWR-SE泵的零件公差对其总效率的影响
4. Fault characterization and testability considerations in multi-valued logic circuits [C] . Abd-El-Barr, M., Al-Sherif, . 1999

机译：多值逻辑电路中的故障表征和可测试性考虑
5. Fault characterization and testability considerations in multi-valued logic circuits [D] . Al-Sharif, Maher Mohammed Mahmoud 1998

机译：多值逻辑电路中的故障表征和可测试性考虑
6. Considerations on the Applicability of Test Methods for Mechanical Characterization of Materials Manufactured by FDM [O] . Amabel García-Domínguez, Juan Claver, Ana María Camacho, 2020

机译：关于FDM制造的材料的机械特性测试方法适用性的考虑
7. Fault characterization and testability considerations inmulti-valued logic circuits [O] . Abd-El-Barr Mostafa, Al-Sherif M., Osman M. 1999

机译：多值逻辑电路中的故障表征和可测试性考虑
8. Applications of Error Correcting Codes in Fault-Tolerant Logic-Design for VLSI Circuits. [R] . Lala, P. K., Martin, H. L. 1992

机译：纠错码在VLsI电路容错逻辑设计中的应用。

Fault characterization and testability considerations in multi-valued logic circuits.

著录项

引文网络

相似文献

相关主题

期刊订阅