A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, making it simple to design. The circuit topology of the DSCL and its operation is explained. Its performance in terms of delay, power, and area is compared to that of conventional static differential logic and dynamic differential logic. SPICE simulations using a 0.18 /spl mu/m technology with a power supply of 1.8 V was utilized to evaluate the performance of the three circuits. Two different sets of simulations were carried out; one with equal input capacitances of all circuits and another with equal circuit delays. For each design, all circuits were optimized for minimum delay. It is shown that at equal input capacitance, the DSCL achieved 40% less delay than the DCVSL at one third the power. Also, at equal delay, the DSCL achieved 20% of the power dissipation of the DCVSL and 78% of the DDCVSL making it the most energy-efficient among the three circuits.
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机译：设计了一个新的差分静态CMOS逻辑（DSCL）系列。新电路是完全静态的，因此设计简单。说明了DSCL的电路拓扑及其操作。将其在延迟，功率和面积方面的性能与传统的静态差分逻辑和动态差分逻辑进行了比较。利用0.18 / spl mu / m技术和1.8 V电源对SPICE进行仿真，以评估这三个电路的性能。进行了两组不同的模拟。一个具有所有电路的相等输入电容，另一个具有相等的电路延迟。对于每种设计，所有电路都经过了优化，以实现最小延迟。结果表明，在输入电容相等的情况下，DSCL的延迟比DCVSL小40％，而功率只有其三分之一。同样，在相等的延迟下，DSCL达到了DCVSL功耗的20％和DDCVSL功耗的78％，使其成为这三个电路中最节能的。
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