This project presents the implementation of 64x64 multi-port dynamically configured SRAM in VHDL (VHSIC hardware description language). It employs isolation nodes and dynamic memory partitioning algorithm to facilitate simultaneous multi-port accesses without duplicating bit-lines. VHDL test-bench is developed to verify the functionality of the dynamically configured memory. Results demonstrate that critical memory operations such as "read miss", "write miss" and "write bypass" can be performed using newly proposed low power, area efficient dynamically configured memory.
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