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Broadcast Mechanism for improving Conditional Branch Prediction in Speculative Multithreaded Processors

机译:改进推测多线程处理器中条件分支预测的广播机制

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摘要

ABSTRACT Many aspects of speculative multithreading have been under constant and crucial research in the recent times with the increased importance in exploiting parallelism in single thread applications. One of the important architectural optimizations that is very pertinent in this scenario is branch prediction. Branch Prediction assumes increased importance for multi-threading systems that execute threads speculatively, since wrong predictions can be much costlier here, in terms of threads, than a few instructions that occupy the pipeline in a uni-processor. Conventional branch prediction techniques have provided increasingly better prediction accuracies for uni-core processing. But the branch prediction itself takes on a whole new dimension when applied to multi-core architectures based on Speculative Multithreading. Dependence on global branch history has helped branch predictors to achieve high prediction accuracy in single thread applications. The discontinuity of global history created at the thread boundaries cripple the performance of branch predictors in a multi-threaded environment. Many studies in the past have tried to address the branch history problem to improve the prediction accuracy. Most of these have been found either to be architecture specific or complex in terms of the hardware needed to recreate or approximate the right history to be given to the threads when they start executing out of order. This hardware overhead increases as the number and size of threads increase thereby limiting the scalability of the algorithms proposed so far. The current thesis takes a different direction and proposes a simple and scalable solution to effectively reduce the misprediction rates in Speculative Multithreaded systems. This is accomplished by making use of a synergistic interaction between threads to boost the inherent biased nature of branches and using less complex hardware to reduce aliasing between branches in the threads. The study proposes a new scheme called the Global Broadcast Buffer scheme to effectively reduce branch mispredictions in Speculative Multithreaded architectures.
机译:摘要近年来,投机性多线程的许多方面一直处于不断而关键的研究之中,在单线程应用程序中利用并行性的重要性日益增加。在这种情况下非常重要的重要体系结构优化之一就是分支预测。对于以推测方式执行线程的多线程系统,分支预测的重要性日益提高,因为就线程而言,错误的预测在这里要比在单处理器中占用管道的几条指令要昂贵得多。传统的分支预测技术已经为单核处理提供了越来越好的预测精度。但是,将分支预测本身应用于基于推测性多线程的多核体系结构时,会带来一个全新的维度。对全局分支历史记录的依赖已帮助分支预测变量在单线程应用程序中实现较高的预测精度。在线程边界处创建的全局历史记录的不连续性削弱了多线程环境中分支预测器的性能。过去许多研究试图解决分支历史问题以提高预测精度。在重新创建或近似在线程开始无序执行时将给予线程的正确历史记录所需的硬件方面,已发现其中大多数都是特定于体系结构的或复杂的。随着线程数量和大小的增加,硬件开销也随之增加,从而限制了目前提出的算法的可扩展性。本论文采取了不同的方向,并提出了一种简单且可扩展的解决方案,以有效降低推测性多线程系统中的误预测率。这是通过利用线程之间的协同交互作用来增强分支的固有偏差性质,以及使用不太复杂的硬件来减少线程中分支之间的混叠来实现的。该研究提出了一种新的方案,称为全局广播缓冲区方案,以有效减少推测性多线程体系结构中的分支错误预测。

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