VHDL Conception and implementation on FPGA of (15,k,d) Reed-Solomon code

摘要

The Reed Solomon code is a detecting corrective code, which play a very important role for the digital transmission. We propose in this paper auddesign and implementation with VHDL langage description. The implementation is realized on a FPGA of Xilinx. The proposed architecture hasudthroughput of 80 Mbps with a frequency of 20 MHZ, and a surface of 1308 CLBs.