Fast dynamically reconfigurable architectures for 1-D and 2-D recursive digital filters

摘要

In this paper, we consider the array processors implementation of the infinite impulse response (11R)1-D and 2-D digital filtersudthat require recursive computations . We use the state space representation to obtain, in a straight forward manner, efficientudimplementation via dynamically switchable systolic arrays (cylindrical type) of 1 -D direct realisation . This direct description leadsudto reduce the computation speed and the throughput rate . In order to improve, in a general way, the throughput rate performanceudof recursive filtering arrays, the solution proposed, in this paper, is based on the CTP decomposition technique of Porter whichudtransforms the matrix-column product on a triple matrix product . It is shown in this work that this technique allows a realisationudof IIR filters via dynamically reconfigurable cylindrical architectures that are much faster. However, this throughput improvementudis obtained in the cost of a hardware complexity . The use of a sparse matrix of the tridiagonal type with the CTP decompositionudpermits a significant improvement of the hardware complexity of recursive filter arrays .