Test-access planning and test scheduling for embedded core-based system chips

摘要

This thesis describes parts of the research work that has been carries out at Philips Research Laboratories, Eindhoven, related to the development of TR-ARCHITECT. TR-ARCHITECT uses a five step heuristic algorithm to design a test architecture. TR-ARCHITECT designs and optimized test architectures with respect to the required ATE vector memory dept and test-application time. TR-ARCHITECT optimizes wrapper and TAM design in conjunction.