This paper presents an area efficient architecturefor quadruple precision division arithmetic on the FPGAplatform. Many application demands for the higher precisioncomputation (like quadruple precision) than the single anddouble precision. Division is an important arithmetic, butrequires a huge amount of hardware resources with increasingprecision, for a complete hardware implementation. So, thispaper presents an iterative architecture for quadruple precisiondivision arithmetic with small area requirement and promisingspeed. The implementation follows the standard processingsteps for the floating point division arithmetic, including processing of sub-normal operands and exceptional case handling. The most dominating part of the architecture, the mantissadivision, is based on the series expansion methodology ofdivision, and designed in an iterative fashion to minimize thehardware requirement. This unit requires a 114x114 bit integermultiplier, and thus, a FPGA based area-efficient integermultiplier is also proposed with better design metrics thanprior art on it. These proposed architectures are implementedon the Xilinx FPGA platform. The proposed quadruple precision division architecture shows a small hardware usage withpromising speed.
展开▼
