On the design and multiplier-less realization of digital IF for software radio receivers with prescribed output accuracy

摘要

This paper studies the design and multiplier-less realization of the digital IF in software radio receivers. The new architecture consists of a compensator for compensating the passband droop of the conventional cascaded integrator and comb (CIC) filter. The passband droop is improved by a factor of four and it can be implemented with four additions using the sum-of-powers-of-two (SOPOT) coefficients. The decimation factor of the multistage decimator is also reduced so that its output can be fed directly to the Farrow structure for sample rate conversion (SRC), eliminating the need for another L-band filter for upsampling. By so doing, the programmable FIR filter can be replaced by a half-band filter placed immediately after the Farrow structure. As the coefficients of this half-band filter, the multistage decimators and the subfilters in the Farrow structure are constants, they can be implemented without multiplication using SOPOT coefficients. As a result, apart from the limited number of multipliers required in the Farrow structure, the entire digital IF can be implemented without any multiplications. A random search algorithm is employed to minimize the hardware complexities of the proposed IF subject to a given specification in the frequency domain and prescribed output accuracy, taking into account signal overflow and round-off noise. Design results are given to demonstrate the effectiveness of the proposed method.