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Design techniques for low power mixed analog-digital circuits with application to smart wireless systems.

机译:适用于智能无线系统的低功耗混合模拟数字电路设计技术。

摘要

This dissertation presents and discusses new design techniques for mixed analog-digital circuits with emphases on low power and small area for standard low-cost CMOS VLSI technology. The application domain of the devised techniques is radio frequency identification (RFID) systems, however the presented techniques are applicable to wide range of mixed mode analog-digital applications. Hence the techniques herein apply to a range of smart wireless or mobile systems. The integration of both analog and digital circuits on a single substrate has many benefits such as reducing the system power, increasing the system reliability, reducing the system size and providing high inter-system communications speed - hence, a cost effective system implementation with increased performance. On the other hand, some difficulties arise from the fact that standard low-cost CMOS technologies are tuned toward maximising digital circuit performance and increasing transistor density per unit area. Usually these technologies have a wide spread in transistor parameters that require new design techniques that provide circuit characteristics based on relative transistor parameters rather than on the absolute value of these parameters. This research has identified new design techniques for mostly analog and some digital circuits for implementation in standard CMOS technologies with design parameters dependent on the relative values of process parameters, resulting in technology independent circuit design techniques. The techniques presented and discussed in this dissertation are (i) applied to the design of low-voltage and low-power controlled gain amplifiers, (ii) digital trimming techniques for operational amplifiers, (iii) low-power and low-voltage Schmitt trigger circuits, (iv) very low frequency to medium frequency low power oscillators, (v) low power Gray code counters, (vi) analog circuits utilising the neuron MOS transistor, (vii) high value floating resistors, and (viii) low power application specific integrated circuits (ASICs) that are particularly needed in radio frequency identification systems. The new techniques are analysed, simulated and verified experimentally via five chips fabricated through the MOSIS service.
机译:本文提出并讨论了针对混合模拟数字电路的新设计技术,该技术重点关注低功耗,小面积的标准低成本CMOS VLSI技术。所设计的技术的应用领域是射频识别(RFID)系统,但是所提出的技术适用于广泛的混合模式模数应用。因此,本文的技术适用于一系列智能无线或移动系统。在单个基板上集成模拟电路和数字电路具有许多优势,例如降低系统功耗,提高系统可靠性,减小系统尺寸并提供高的系统间通信速度-因此,可实现具有成本效益的系统实现,并具有更高的性能。另一方面,由于标准低成本CMOS技术已朝着最大化数字电路性能和增加单位面积晶体管密度的方向发展,因此产生了一些困难。通常,这些技术在晶体管参数中分布广泛,需要新的设计技术来提供基于相对晶体管参数而不是基于这些参数的绝对值的电路特性。这项研究确定了针对大多数模拟电路和一些数字电路的新设计技术,这些技术可以在标准CMOS技术中实现,其设计参数取决于工艺参数的相对值,从而形成了与技术无关的电路设计技术。本文提出和讨论的技术(i)应用于低压和低功率受控增益放大器的设计,(ii)用于运算放大器的数字微调技术,(iii)低功率和低压施密特触发器电路,(iv)极低频至中频低功率振荡器,(v)低功率格雷码计数器,(vi)利用神经元MOS晶体管的模拟电路,(vii)高值浮动电阻和(viii)低功率应用射频识别系统中特别需要的专用集成电路(ASIC)。通过通过MOSIS服务制造的五种芯片,对新技术进行了分析,仿真和实验验证。

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