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High performance RF CMOS VCOs for wireless communication.

机译:用于无线通信的高性能RF CmOs VCO。

摘要

This thesis is dedicated to develop a set of general and systematic techniques to design and produce high performance monolithic CMOS VCOs to use in modem wireless front-end chips. In general, there are four topics covered in this research work. First, existing oscillator phase noise estimation theories are discussed. Some of these theories lead to simple and rough estimation of the phase noise, while some forms the basis for more complicated and accurate phase noise estimation performed by modem CAD tools. Second, the operation and noise performance of a number of differential LC tuned VCO topologies are investigated in detail. Some common misconceptions associated with cross-coupled oscillators, including the incorrect linear oscillation amplitude expressions, nonexistence of a VCO bias region called voltage-limited region, and the non-apparent topological advantage of the complementary topology are addressed. AIso the noise sources associated with differential LC tuned VCOs are identified and investigated. Upconversion processes of low frequency flicker noise through various up conversion processes are discussed. Third, based on the understandings acquired from the differential Le tuned oscillator analyses, a set of new optimization techniques is developed. These techniques allow for design of the best performing VCO realizable for a given process technology, chip area, and power budget. A new geometric monolithic planar spiral inductor optimization technique, an efficient way to trade between power consumption and phase noise performance via L/C ratio scaling, appropriate sizing of the cross-coupled transistors, and a low-power, low-noise current biasing technique are among the VCO optimization techniques developed in this research work. Lastly, the VCO optimization techniques developed are tested and validated by fabricating a number of VCOs using two different modem CMOS process technologies and analyzing their performances. The performances of these VCOs are then compared against the state-of-the-art monolithic VCOs reported in the literature. The comparison is not limited to CMOS VCOs, but extends to other competing process technologies such as bipolar technology. The comparison clearly shows the superiority of some of the VCOs designed and fabricated in this research work.
机译:本文致力于开发一套通用的系统技术,以设计和生产用于调制解调器无线前端芯片的高性能单片CMOS VCO。通常,此研究工作涵盖四个主题。首先,讨论现有的振荡器相位噪声估计理论。这些理论中的一些导致对相位噪声的简单而粗略的估计,而另一些则构成了由现代CAD工具执行的更为复杂和准确的相位噪声估计的基础。其次,详细研究了许多差分LC调谐VCO拓扑的操作和噪声性能。解决了与交叉耦合振荡器相关的一些常见误解,包括不正确的线性振荡幅度表达式,不存在被称为电压限制区的VCO偏置区以及互补拓扑的非表观拓扑优势。因此,识别和研究了与差分LC调谐VCO相关的噪声源。讨论了通过各种上变换过程对低频闪烁噪声进行上变换的过程。第三,基于从差分Le调谐振荡器分析获得的理解,开发了一套新的优化技术。这些技术允许设计出对于给定的处理技术,芯片面积和功率预算可实现的最佳性能的VCO。一种新的几何单片平面螺旋电感器优化技术,一种通过L / C比例缩放在功耗和相位噪声性能之间进行权衡的有效方法,交叉耦合晶体管的适当尺寸以及低功耗,低噪声电流偏置技术是这项研究工作中开发的VCO优化技术之一。最后,通过使用两种不同的调制解调器CMOS工艺技术制造许多VCO并分析其性能,来测试和验证开发的VCO优化技术。然后将这些VCO的性能与文献中报道的最新的整体式VCO进行比较。比较不仅仅限于CMOS VCO,还扩展到了其他竞争工艺技术,例如双极技术。比较清楚地表明了本研究工作中设计和制造的某些VCO的优越性。

著录项

  • 作者

    Kim Tae Youn;

  • 作者单位
  • 年度 2005
  • 总页数
  • 原文格式 PDF
  • 正文语种
  • 中图分类
  • 入库时间 2022-08-20 21:03:07

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