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Effects of alternating current voltage amplitude and oxide capacitance on mid-gap interface state defect density extractions in In0.53Ga 0.47As capacitors

机译:交流电压幅值和氧化物电容对In0.53Ga 0.47as电容器中间隙界面态缺陷密度提取的影响

摘要

This work looks at the effect on mid-gap interface state defect density estimates for In0.53Ga0.47As semiconductor capacitors when different AC voltage amplitudes are selected for a fixed voltage bias step size (100 mV) during room temperature only electrical characterization. Results are presented for Au/Ni/Al2O3/In0.53Ga0.47As/InP metal–oxide–semiconductor capacitors with (1) n-type and p-type semiconductors, (2) different Al2O3 thicknesses, (3) different In0.53Ga0.47As surface passivation concentrations of ammonium sulphide, and (4) different transfer times to the atomic layer deposition chamber after passivation treatment on the semiconductor surface—thereby demonstrating a cross-section of device characteristics. The authors set out to determine the importance of the AC voltage amplitude selection on the interface state defect density extractions and whether this selection has a combined effect with the oxide capacitance. These capacitors are prototypical of the type of gate oxide material stacks that could form equivalent metal–oxide–semiconductor field-effect transistors beyond the 32 nm technology node. The authors do not attempt to achieve the best scaled equivalent oxide thickness in this work, as our focus is on accurately extracting device properties that will allow the investigation and reduction of interface state defect densities at the high-k/III–V semiconductor interface. The operating voltage for future devices will be reduced, potentially leading to an associated reduction in the AC voltage amplitude, which will force a decrease in the signal-to-noise ratio of electrical responses and could therefore result in less accurate impedance measurements. A concern thus arises regarding the accuracy of the electrical property extractions using such impedance measurements for future devices, particularly in relation to the mid-gap interface state defect density estimated from the conductance method and from the combined high–low frequency capacitance–voltage method. The authors apply a fixed voltage step of 100 mV for all voltage sweep measurements at each AC frequency. Each of these measurements is repeated 15 times for the equidistant AC voltage amplitudes between 10 mV and 150 mV. This provides the desired AC voltage amplitude to step size ratios from 1:10 to 3:2. Our results indicate that, although the selection of the oxide capacitance is important both to the success and accuracy of the extraction method, the mid-gap interface state defect density extractions are not overly sensitive to the AC voltage amplitude employed regardless of what oxide capacitance is used in the extractions, particularly in the range from 50% below the voltage sweep step size to 50% above it. Therefore, the use of larger AC voltage amplitudes in this range to achieve a better signal-to-noise ratio during impedance measurements for future low operating voltage devices will not distort the extracted interface state defect density.
机译:这项工作着眼于在室温下仅通过电特性表征为固定电压偏置步长大小(100 sizemV)选择不同的交流电压幅度时,对In0.53Ga0.47As半导体电容器对中间间隙界面状态缺陷密度估计的影响。给出了具有(1)n型和p型半导体,(2)不同Al2O3厚度,(3)In0.53Ga0不同的Au / Ni / Al2O3 / In0.53Ga0.47As / InP金属氧化物半导体电容器的结果.47为硫化铵的表面钝化浓度,以及(4)在半导体表面进行钝化处理后到原子层沉积室的转移时间不同,从而证明了器件特性的横截面。作者着手确定交流电压幅度选择对界面态缺陷密度提取的重要性,以及该选择是否与氧化物电容共同作用。这些电容器是典型的栅极氧化物材料叠层的类型,可以形成超过32nm工艺节点的等效金属氧化物半导体场效应晶体管。作者们并未尝试在这项工作中获得最佳比例的等效氧化物厚度,因为我们的重点是准确提取器件性能,从而可以研究和降低高k / III-V半导体界面的界面态缺陷密度。未来设备的工作电压将降低,有可能导致交流电压幅度的降低,这将迫使电响应的信噪比降低,因此可能导致阻抗测量的准确性降低。因此,对于使用此类阻抗测量的未来设备,尤其是与根据电导方法和高低频电容-电压组合方法估算的中间间隙界面状态缺陷密度有关的电特性提取的准确性方面,存在一些问题。作者对每个交流频率下的所有电压扫描测量均采用100 mV的固定电压步进。对于10 mV至150 mV之间的等距交流电压幅度,将这些测量中的每一个重复15次。这提供了所需的AC电压幅度与步长之比(从1:10到3:2)。我们的结果表明,尽管氧化物电容的选择对于提取方法的成功与准确度都至关重要,但中间间隙界面态缺陷密度提取对使用的交流电压幅度并不过于敏感,而与氧化物电容的大小无关。用于提取中,尤其是在电压扫描步长以下50%到电压扫描步长以下50%的范围内。因此,在此范围内使用较大的AC电压幅度以在阻抗测量期间为将来的低工作电压设备获得更好的信噪比,不会使提取的界面状态缺陷密度失真。

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