The design and implementation of high purity, high speed and power efficient clock generation Integrated Circuits continue to be one the greatest challenges facing IC designers today. In order to address this challenge, this thesis considers the modeling and design of two fundamental clock generation circuits – the VCO and PLL.An improved ring oscillator topology is proposed which has the advantage of an ultra wide tuning range. A novel noise aware ring oscillator model is also proposed which links the noise performance of the oscillator to its transistor dimensions giving insight to the design procedure. The use of this VCO model in a noise-aware PLL model allows the trade-off between noise performance and the loop bandwidth to be quantified accurately. From further analysis of the proposed PLL model, a novel PLL structure has been designed which is extremely successful at reference spur suppression.Simulation results based on the proposed model and foundry BSIM3v3 models are provided for all the VCO and PLL designs. To validate the proposed VCO topology and VCO model, two prototype chips have been fabricated and measured results show close agreement with theoretical analysis and simulation
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