Low-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors at supply voltages below Vccmin.\udRecent proposals provide a rather low fault-coverage due to the fault coverage/overhead trade-off. We propose a new fault-\udtolerant L1 cache, which combines SRAM and eDRAM cells in L1 data caches to provide 100% SRAM hard-error fault coverage.\udResults show that, compared to a conventional cache and assuming 50% failure probability at low-power mode, leakage\udand dynamic energy savings are by 85% and 62%, respectively, with a minimal impact on performance.
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