High-performance and Low-power Clock Network Synthesis in the Presence of Variation.

摘要

Semiconductor technology scaling requires continuous evolution of all aspects of physicaldesign of integrated circuits. Among the major design steps, clock-network synthesishas been greatly affected by technology scaling, rendering existing methodologies inadequate.Clock routing was previously sufficient for smaller ICs, but design difficulty andstructural complexity have greatly increased as interconnect delay and clock frequency increasedin the 1990s. Since a clock network directly influences IC performance and oftenconsumes a substantial portion of total power, both academia and industry developed synthesismethodologies to achieve low skew, low power and robustness from PVT variations.Nevertheless, clock network synthesis under tight constraints is currently the least automatedstep in physical design and requires significant manual intervention, underminingturn-around-time. The need for multi-objective optimization over a large parameter spaceand the increasing impact of process variation make clock network synthesis particularlychallenging. Our work identifies new objectives, constraints and concerns in the clock-network synthesisfor systems-on-chips and microprocessors. To address them, we generate novelclock-network structures and propose changes in traditional physical-design flows. Wedevelop new modeling techniques and algorithms for clock power optimization subjectto tight skew constraints in the presence of process variations. In particular, we offerSPICE-accurate optimizations of clock networks, coordinated to reduce nominal skew below5 ps, satisfy slew constraints and trade-off skew, insertion delay and power, whiletolerating variations. To broaden the scope of clock-network-synthesis optimizations, wepropose new techniques and a methodology to reduce dynamic power consumption by6.8%-11.6% for large IC designs with macro blocks by integrating clock network synthesiswithin global placement. We also present a novel non-tree topology that is 2.3x morepower-efficient than mesh structures. We fuse several clock trees to create large-scale redundancyin a clock network to bridge the gap between tree-like and mesh-like topologies.Integrated optimization techniques for high-quality clock networks described in this dissertationstrong empirical results in experiments with recent industry-released benchmarksin the presence of process variation. Our software implementations were recognized withthe first-place awards at the ISPD 2009 and ISPD 2010 Clock-Network Synthesis Contestsorganized by IBM Research and Intel Research.