Hybrid Synchronous/Stationary Reference Frame Filtering based PLL

摘要

Designing an effective phase-locked loop (PLL) for three-phase applications is the objective of this paper. The designed PLL structure is able to provide an accurate estimation of grid voltage frequency and phase even in the presence of all harmonic components of both positive and negative sequences and dc offset in its input. It addition to offer a high disturbance rejection capability, the suggested PLL structure has a fast transient response and provides a settling time of around two cycles of fundamental frequency. The effectiveness of suggested PLL structure is confirmed using numerical results.